Field of the Invention
Embodiments of the present invention may relate to optical routing elements and optical routing arrays.
Background
The International Technology Roadmap for Semiconductors highlights key interconnects challenges for next-generation microprocessors and computing systems. The roadmap suggests that the most difficult challenges in the near term include the rapid introduction of interconnect processes compatible with device roadmaps, coupled with fine dimensional control and providing good mechanical stability and thermal budget. Further, the interconnect technologies should be able to meet performance requirements and manufacturing targets by leveraging low-cost conventional mass fabrication techniques and provide solutions to address global wiring scaling issues. The continued push towards finer geometries, higher frequencies and larger chip sizes increasingly exposes the disparity between interconnect needs and projected interconnect performance.
In order to realize reconfigurable computing, field programmable gate arrays (FPGAs) are vital, and hence there is a need to mimic neocortic interconnect architectures, namely 3D routing with exceedingly high bandwidth density. In that regard, realization of 2D and 3D interconnect routing topologies that use similar or compatible materials that achieve better scale of integration and alignment tolerance would be extremely beneficial.
Concepts for planar optical routing in a single layer of opto-electronic interconnects using a planar self-collimation photonic crystal have been proposed, as have a full three-dimensional interconnect using buried silicon micro-machining techniques. In the case of the slab, flip-chips are bonded onto an underlying CMOS substrate that contains the appropriate driver and receiver circuitry to input and output optical signals to the slab. The slab also contains optical sources and receivers that serve to generate and detect light. Within the slab, a self-collimation photonic crystal serves as the interconnect medium between the source and detector. In the case of the buried silicon optical interconnect technology, which may be referred to as the sub-surface silicon optical bus (S3B), direct integration into the CMOS process is easily achieved. The direction of propagation of the various optical signals as well as their destinations is achieved via electro-optical switches
Electro-optical switches are key components of such photonic integrated circuits, yet only one proposal for implementing such switches—a resonator device—has appeared in the literature. The reconfigurable computing proposals may therefore benefit from additional options in electro-optical switches.